The present application relates to display devices, methods for driving a display device, and electronic apparatus, and particularly to a display device having a memory to store image data in the pixel, a method for driving this display device, and electronic apparatus having this display device.
Among display devices are ones having a memory to store image data in the pixel. In e.g. a display device having a built-in memory in the pixel, displaying by an analog display mode and displaying by a memory display mode can be realized. The analog display mode refers to a display mode in which the grayscale of the pixel is displayed in an analog manner. The memory display mode refers to a display mode in which the grayscale of the pixel is displayed in a digital manner based on binary information (logic “1”/“0”) stored in the memory in the pixel.
In the memory display mode, it is unnecessary to carry out operation of writing the signal potential reflecting the grayscale with the frame cycle because information retained in the memory is used. Therefore, in the memory display mode, the power consumption is lower than that in the analog display mode, in which it is necessary to carry out operation of writing the signal potential reflecting the grayscale with the frame cycle.
As a related-art display device capable of both displaying by the analog display mode and displaying by the memory display mode, a display device in which a static random access memory (SRAM) is used as the built-in memory in the pixel is known (refer to e.g. Japanese Patent Laid-Open No. 2009-98234).
FIG. 21 shows one example of a pixel circuit of a liquid crystal display device according to a related-art example using the SRAM as the memory in the pixel. A pixel 90 in the liquid crystal display device according to the present related-art example has liquid crystal capacitance 91, holding capacitance 92, an SRAM 93, and five switching transistors 94 to 98. To the pixel 90, a signal potential Vsig reflecting the grayscale or a potential VXCS different from a common potential VCOM is selectively given via a signal line 99.
The liquid crystal capacitance 91 means the capacitance generated between a pixel electrode and a counter electrode formed opposed to the pixel electrode when a liquid crystal is enclosed between the pixel electrode and the counter electrode. The common potential VCOM is given to the counter electrode of the liquid crystal capacitance 91 in common to all pixels. The pixel electrode of the liquid crystal capacitance 91 is electrically connected to one electrode of the holding capacitance 92 in common. The holding capacitance 92 holds the signal potential Vsig reflecting the grayscale. A CS potential VCS that is almost the same as the common potential VCOM is given to the other electrode of the holding capacitance 92.
The SRAM 93 is composed of two CMOS inverters provided between a positive-side supply potential VRAM and a negative-side supply potential VSS. The input terminal of one of these two CMOS inverters is connected to the output terminal of the other in common. The input terminal of the other is connected to the output terminal of one in common.
Of two CMOS inverters configuring the SRAM 93, one CMOS inverter is composed of a PchMOS transistor 931 and an NchMOS transistor 932 that are connected in series between the supply potential VRAM and the supply potential VSS and have gate electrodes connected in common. The other CMOS inverter is composed of a PchMOS transistor 933 and an NchMOS transistor 934 that are connected in series between the supply potential VRAM and the supply potential VSS and have gate electrodes connected in common.
Five switching transistors 94 to 98 are formed of e.g. thin film transistors. The conductive/non-conductive state of the switching transistors 94 and 95 is controlled by a control signal CTL1. Specifically, the switching transistors 94 and 95 become the conductive state in response to the control signal CTL1 that becomes the active (higher potential) state in writing of the signal potential Vsig reflecting the grayscale to the holding capacitance 92.
The switching transistor 96 becomes the conductive state in writing of the signal potential Vsig reflecting the grayscale in the analog display mode or in writing of the potential VXCS different from the common potential VCOM in the memory display mode. The switching transistor 97 becomes the conductive state in writing of the CS potential VCS, which is almost the same as the common potential VCOM given to the counter electrode of the liquid crystal capacitance 91, to the holding capacitance 92 in the memory display mode.
The held potential of the SRAM 93 is used for control of the conductive/non-conductive state of the switching transistors 96 and 97. In this circuit example, the switching transistor 97 is in the non-conductive state when the switching transistor 96 is in the conductive state, and the switching transistor 97 is in the conductive state when the switching transistor 96 is in the non-conductive state.
The conduction control of the switching transistor 98 is carried out by a control signal CTL2 that becomes the active (higher potential) state in writing of a control potential to the SRAM 93. Specifically, the switching transistor 98 becomes the conductive state in response to the control signal CTL2 that becomes the active state in writing of the signal potential Vsig to the SRAM 93 in the analog display mode or in writing of the potential VXCS to the SRAM 93 in the memory display mode.
Although the pixel circuit example in which the SRAM 93 is provided for each pixel 90 based on a one-to-one correspondence relationship is shown in FIG. 21, it is also possible to employ a configuration in which one SRAM 93 is provided (shared) in common to the plural pixels 90.
As one example, as shown in FIG. 22, it is also possible to provide one SRAM 93 in common to e.g. sub-pixels 90R, 90G, and 90B of red (R), green (G), and blue (B) configuring one pixel 90 in a liquid crystal display device for color displaying. Although holding capacitances 92R, 92G, and 92B of the sub-pixels 90R, 90G, and 90B are shown in FIG. 22, diagrammatic representation of the respective liquid crystal capacitances 91 of the sub-pixels 90R, 90G, and 90B is omitted for simplification of the diagram.
In the case of employing the configuration in which one SRAM 93 is shared by the sub-pixels 90R, 90G, and 90B, the switching transistor 94 (94R, 94G, 94B) is disposed for each of the sub-pixels 90R, 90G, and 90B. The conductive/non-conductive state of these switching transistors 94R, 94G, and 94B is controlled in a time-division manner by control signals CTL1(R), CTL1(G), and CTL1(B) corresponding to the respective colors.